FIG. 1 schematically shows a configuration where two interfaces IF1 and IF2 are connected through a bidirectional serial link. The notations and definitions hereinafter are provided with reference to the interface IF1 or “local” interface, the interface IF2 being the “remote” interface. Any bidirectional serial link typically includes a receiver line Rx, a transmission line Tx and a ground line (not shown). According to the standards or protocols specifying the interfaces, other lines may be provided, such as a clock line, data flow management lines, etc.
The outgoing signal on the Tx line is supplied by an amplifier 10, commonly referred to as a “buffer”, often in the form of an inverter. The incoming signal on the Rx line is processed by a logic level discriminator 12, for example a hysteresis comparator or “Schmitt-trigger”. The elements 10 and of the interface are adapted to the specifications of the communication standard used. A standard usually specifies a peak to peak voltage for the signals and operating frequencies. The voltage values are provided with a margin of tolerance.
The local interface IF1 is supplied between a ground Vss1 and a voltage Vdd1 while the remote interface IF2 is supplied between a ground Vss2 and a voltage Vdd2. The grounds Vss1 and Vss2 are generally set at the same level through the ground line, not shown, of the serial link. The supply voltages Vdd1 and Vdd2 may be different.
In many cases, the two interfaces IF1 and IF2 are designed specifically to use the same communication protocol. If the voltages Vdd1 and Vdd2 do not correspond to the voltage level required by the protocol, the interfaces may integrate voltage regulators that supply elements 10 and 12 of the interfaces with the required voltage level. Thus, each inverter 10 supplies a logic signal having the required amplitude, even if the signal at its input has a different amplitude, and each discriminator 12 sets its triggering points at the same levels, so that homologous interfaces behave consistently with each other, and comply if necessary with the standard used.
The consistency of the homologous interfaces depends on how well the power levels of these interfaces match. Although standards recommend voltage levels with a margin of tolerance, satisfying these margins is not always guaranteed.
It is thus desired that homologue interfaces operate together satisfactorily even if the supply voltages of the interfaces vary by an unknown factor. U.S. Pat. No. 8,698,543 and patent application EP 1231563 offer solutions satisfying this need.
FIG. 2 shows a local interface IF1, as described in patent application EP 1231563, able to automatically adapt to the operating conditions of the remote interface IF2.
The interface IF1 comprises elements of a conventional interface, such as an amplifier or inverter 10 providing the output signal Tx and the logic level discriminator 12 processing the incoming signal Rx.
The interface IF1 further comprises a peak detector 14 connected to store the peak level of the input signal Rx. The peak level Vdd2′ established by the circuit 14 is replicated by a low impedance voltage follower 16. The output of the follower supplies the high sides of elements 10 and 12 of the interface, the low sides being powered by the ground line Vss1.
With this configuration, when the input signal Rx has a high level, which corresponds in principle to the power level Vdd2 of the remote interface IF2, the elements 14 and 16 establish the supply voltage of the elements 10 and 12 to this same level or a level close thereto, noted Vdd2′. Thus, the comparison thresholds of the discriminator 12 naturally establish to values adapted to the input signal Rx, and the inverter 10 produces an output signal Tx having an amplitude suiting the remote interface. This operation is obtained irrespective of the supply voltage of the remote interface or the amplitude of the input signal Rx. It follows that the local interface automatically adapts to the power supply level of the remote interface.
In some applications, especially if the interfaces do not need to be fast, the inverter 10 is a single N-channel MOS transistor connected in “open drain”. In other words, this transistor is not supplied from the high side (Vdd2′) of the local interface. Instead, the remote interface includes a so-called pull-up resistor, which connects the Tx line to supply line Vdd2.
The peak detector used in these circuits generally comprises an RC circuit and a diode, elements that may occupy significant surface area in certain applications.